1. Field
Embodiments of the invention relate to an inverter device which can reduce a waveform distortion of an output voltage even when there is a period in which a current of a phase lagging behind that of an alternating current output voltage flows.
2. Description of Related Art
A three-level inverter device, one phase of which is configured by connecting two switching elements to each of which a diode is connected in anti-parallel and one end of a bidirectional switch at the connection point of these two switching elements, is known (PTL 1). In the three-level inverter device, two switching elements of each phase are connected in series across a direct current power source. Also, the other end of the bidirectional switch is connected to the intermediate potential point of the direct current power source. Further, each element of the three-level inverter device performs an on/off operation based on a control signal pulse-width modulated using an output voltage command and a carrier signal with a higher frequency than the frequency of the output voltage command. As a result of this, the three-level inverter device outputs a pulse-width modulated phase voltage. This kind of three-level inverter device is described in PTL 2.
FIG. 8 is a diagram illustrating a configuration of a U-phase circuit of this kind of three-level inverter device. In FIG. 8, 1 is a direct current power source, 2 is an inverter circuit, 3 is a filter circuit, and 4 is a load. The direct current power source 1 is a power source wherein a positive side power source Psp and a negative side power source Psn are connected in series. The output terminals of the direct current power source 1 are a positive side terminal P of the positive side power source Psp, a negative side terminal N of the negative side power source Psn, and a neutral terminal C which is the connection point of the positive side power source Psp and negative side power source Psn. The positive side terminal P outputs a positive voltage V1 of the positive side power source Psp. The negative side terminal N outputs a negative voltage V2 of the negative side power source Psn. The neutral terminal C outputs a zero voltage Vz (not illustrated) which is the intermediate voltage of the direct current power source 1.
The inverter circuit 2 is configured of switching elements Q1 and Q2 and switch elements S1 and S2. The switching elements Q1 and Q2 are connected in series and connected across the direct current power source 1. The connection point of the switching elements Q1 and Q2 is an output terminal U which outputs an alternating current voltage Vout. The switch elements S1 and S2, being connected in anti-parallel, configure a bidirectional switch BS. The bidirectional switch BS is connected between the neutral terminal C and the output terminal U. The filter circuit 3 is a circuit formed by connecting a reactor Lf and a capacitor Cf in series. The filter circuit 3 is connected between the output terminal U and the neutral terminal C. The load 4 is connected across the capacitor Cf. A sinusoidal load voltage Vload obtained by removing a harmonic component from the output voltage Vout of the inverter circuit 2 is output across the capacitor Cf.
Firstly, a description will be given of an operation of the inverter circuit 2 when outputting the positive load voltage Vload. FIG. 9 is a chart showing the relationship between the control signal of each element and the output voltage Vout. Each element is turned on when the control signal is at a high level (hereinafter “H”), and is turned off when the control signal is at a low level (hereinafter “L”).
FIG. 9 part (a) shows a temporal change in a first pulse width modulation signal (a PWM signal 1). The PWM signal 1 is a signal which is a reference for generating the control signals of the switching element Q1 and switch element S2. The PWM signal 1 alternates between H and L. The control signal of the switching element Q1 switches to H or L in synchronism with the PWM signal 1 (FIG. 9 part (c)). The control signal of the switch element S2 is a signal which is inverted between H and L of the PWM signal 1 and to which dormant periods Td are added (FIG. 9 part (f)). The dormant periods Td are periods for turning off both the switching element Q1 and the switch element S2 in order to prevent a short circuit of the switching element Q1 and switch element S2.
FIG. 9 part (b) shows a temporal change in a second pulse width modulation signal (a PWM signal 2). The PWM signal 2 is a signal which is a reference for generating the control signals of the switching element Q2 and switch element S1. The PWM signal 2 is always at L in this period. The control signal of the switching element Q2 is always at L in response to the PWM signal 2 (FIG. 9 part (d)). The control signal of the switch element S1 is always at H in response to the signal which is inverted between H and L of the PWM signal 2 (FIG. 9 part (e)).
When the individual elements perform an on/off operation based on the heretofore described control signals, a positive pulse train voltage Vout is output between the output terminal U and the neutral terminal C (hereinafter “between the terminals U and C”). The voltage Vout is pulse-width modulated, and the amplitude thereof is of the voltage V1 of the direct current power source Psp.
The operation of the U-phase circuit when outputting a negative voltage only has to be considered so as to interchange the operations of the PWM signal 1 and PWM signal 2, interchange the control signals of the switching element Q1 and switching element Q2, and furthermore, interchange the control signals of the switch element S1 and switch element S2. Further, when each element performs an on/off operation based on the control signal, a negative pulse train voltage Vout is output between the terminals U and C. The voltage Vout is pulse-width modulated, and the amplitude thereof is of the voltage V2 of the direct current power source Psn.
As heretofore described, the output voltage Vout is a pulse-width modulated pulse train voltage and includes a harmonic component. The harmonic component included in the output voltage Vout is removed by the filter circuit 3. In the same way, a harmonic component included in an output current Iout of the inverter circuit 2 is removed by the filter circuit 3. As a result of this, the sinusoidal alternating current voltage Vload is applied to the load 4. Also, a sinusoidal alternating current Iload flows through the load 4.